The present invention relates to semiconductor integrated circuits, and more particularly to semiconductor integrated circuits including an electrostatic protection device.
With recent increased miniaturization and integration density in semiconductor integrated circuit processes, reduction in size has also been desired for electrostatic protection devices for protecting semiconductor integrated circuits from static electricity carried by human bodies, machines, etc. In order to protect the semiconductor integrated circuits from static electricity, the electrostatic protection devices are connected to an input/output (I/O) terminal and a power supply terminal of the semiconductor integrated circuits. A bipolar or metal oxide semiconductor (MOS) transistor structure, etc. is used in the electrostatic protection devices (see, e.g., Japanese Patent Publication No. 2004-335634).
A conventional electrostatic protection device using an npn bipolar transistor structure will be described with reference to FIGS. 21-22.
As shown in FIG. 21, a p-type diffusion layer 105 serving as a base of an npn transistor is formed in the upper part of an n-type low concentration semiconductor substrate 103, and an n-type high concentration diffusion layer 106 serving as an emitter of the npn transistor is formed in the upper part of the p-type diffusion layer 105. A p-type high concentration diffusion layer 107 serving as a base contact is formed in a region separated from the n-type high concentration diffusion layer 106 in the upper part of the p-type diffusion layer 105. An n-type high concentration diffusion layer 108, serving as a collector contact and having about the same depth as the n-type high concentration diffusion layer 106, is formed in a region laterally separated from the p-type diffusion layer 105 by a predetermined distance in the upper part of the n-type low concentration semiconductor substrate 103. A local oxidation of silicon (LOCOS) film 121 is formed between the p-type diffusion layer 105 and the n-type high concentration diffusion layer 108 in the upper part of the n-type low concentration semiconductor substrate 103. An emitter electrode 131 forms an ohmic connection to the n-type high concentration diffusion layer 106, a base electrode 132 forms an ohmic connection to the p-type high concentration diffusion layer 107, and a collector electrode 133 forms an ohmic connection to the n-type high concentration diffusion layer 108. The base electrode 132 and the emitter electrode 131 are short-circuited together via an aluminum interconnect, etc., and are connected to the lowest potential such as the ground (GND). The collector electrode 133 is connected via an aluminum interconnect, etc. to an input/output (I/O) pad (PAD) 130 and an internal circuit 140 that are formed on a substrate of a semiconductor integrated circuit.
As shown in FIG. 22, when positive surge charge due to static electricity, etc. is applied from the I/O PAD 130 to the collector electrode 133 of the npn transistor having the above configuration, a current produced by avalanche breakdown flows between the collector and the base (a collector-base breakdown voltage: BVCBO). Then, the base potential increases to the operating voltage of the npn transistor, and the npn transistor starts a bipolar operation (a trigger point: a trigger voltage Vt1, a trigger current It1). When the current increases, the number of electrons injected from the n-type high concentration diffusion layer 106 into a region located below the n-type high concentration diffusion layer 106 in the n-type low concentration semiconductor substrate 103 becomes excessive as this region has a low impurity concentration. In order to neutralize the excess electrons, holes are injected from the p-type diffusion layer 105 into this region, whereby this region functions as a base. At this time, since this region is not an n-type layer but a neutral region, the collector potential decreases from the trigger voltage Vt1 to a holding voltage Vh between the collector and the emitter, which is dependent on the current gain (hFE) of the npn transistor at this time. In this npn transistor structure, the current path between the collector and the emitter is short because the current flows near the surface of the n-type low concentration semiconductor substrate 103. That is, since the base width is narrow, and hFE is high at this time, the holding voltage Vh decreases significantly as compared to the trigger voltage Vt1. Then, the collector potential increases from the holding voltage Vh to a breakdown voltage Vt2 according to the collector resistance that is dependent on the n-type high concentration diffusion layer 108. If the current further increases thereafter, thermal runaway is caused by heat generated at the end on the base side of the n-type high concentration diffusion layer 108 due to current concentration, resulting in breakdown (a breakdown point: a breakdown voltage Vt2, breakdown endurance It2).
In addition, electrostatic protection devices suitable for protecting high breakdown voltage elements have been proposed in Japanese Patent Publication No. 2007-242923. These electrostatic protection devices maintain a high holding voltage by using such a structure that increases an apparent base width.